Design Verification Engineer - #1769583

Design Verification:

• Create coverage driven verification plan document.


• Create UVM verification environment.


• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)


• The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems


• Run regressions, debug test failures and file bug report as needed.


• Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps.


• Provide verification report as needed to show all implemented tests passing on the RTL.


• Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases